Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Select

A concurrent statement which assigns one of several expressions to a signal, depending on the value of the expression at the top. Equivalent to a process containing a case statement.

Syntax

  [Label:] with Expression select
    Target <= [Options]
      Expression [after TimeExpression] when Choices,
      Expression [after TimeExpression] when Choices,
      ... ;

  Target = {either} SignalName Aggregate

  Options = {either}
  guarded
  transport
  reject TimeExpression inertial

  Choices = Choice | ...

  Choice = {either}
  ConstantExpression
  Range
  others  {the last choice}
    

Where

architecture-begin--end block-begin--end generate-begin--end

Rules

The reserved word guarded may only appear in a signal assignment within a guarded block. A guarded assignment only executes when the guard expression on the surrounding block is true. Every case of the Expression at the top must be covered once and only once by the choices. An Expression on the right hand side may be replaced by the reserved word unaffected.

Synthesis

Selected signal assignments are synthesized to combinational logic. The Expressions on the right hand side are multiplexed onto the Target signal.

Tips

Conditional and selected signal assignments are a good way to describe combinational logic in Register Transfer Level descriptions.

Example

  Mux: with S select
    F <= A when "000",
         B when "001",
         C when "010" | "011" | "100",
         D when others;
    

See Also

Signal Assignment, Conditional Assignment, Case, Block